1. Field of the Invention
This invention relates to a process for planarizing group II-VI insulators and to an etching procedure and etchant therefor.
2. Brief Description of the Prior Art
In multilayer semiconductor devices, excess topology or non-planarity is often introduced during fabrication by underlying partial structures, particularly levels of metal, such as metal lines or buses. This causes insulator thereover to generally conform to the topology therebelow and introduce the same non-planarity therein. A result is that stress is introduced into the device and crevices resulting from the non-planarity collect unwanted particles, both of which are causes for device degradation, such as, for example, short circuits and a concomitant reduction in ultimate yield.
In the prior art silicon technology, non-planarity problems are alleviated by a procedure known as resist and etch-back wherein a resist or other conformal material is spun over the non-planar layer having a thickness much greater than the amount of non-planarity with a resulting planar or flat resist surface, regardless of the topology thereunder. The resist is than etched back with an etchant which etches the non-planar layer thereunder at the same etch rate as the resist until all of the resist has been removed and the former non-planar layer thereunder has been planarized.
No equivalent procedure is known for use in conjunction with group II-VI semiconductor compositions, apparently because the chemistry involved is entirely different from that involving silicon technology and the procedures used in conjunction with silicon technology are not transferable to group II-VI technology. It is therefore apparent that an entirely new procedure is required for planarization of group II-VI compositions.